Vedic Maths is the ancient system of Indian mathematics. It has been extracted from 16sutras. Out of these 16 sutras, only one of these sutras named Urdhva Tiryagbhyam is used in this project. Urdhva is meant for Vertical and Tiryagbhyam is meant for the Crosswise multiplication process. This project is about designing of 8-, 16-, 32-, 64-bit Vedic multiplier with modified architecture and improved performance in comparison with a recent journal on 32-bit Vedic multiplier. And also 64-bit Vedic multiplier according to the reference journal is designed. The design of the proposed 64-bit Vedic multiplier consists of three stages, the first stage consists of four 32-bit Vedic multipliers, second stage has 96-bitcarry save adder and 95-bit modified carry skip adder in which internal stages consists of 8-bit and 16-bit Sklansky adders. and this design is implemented in XilinxISE14.7 and obtained a delay of 19.707ns, number of Slice LUT’s of 6989, power consumption of 111mW. The selected device in Xilinx14.7ISE is xc7k70t-3fbg484 from the Kintex-7 family. And also the reference design(64-bit Vedic multiplier) is calibrated using XilinxISE14.7 with the same device and obtained a delay of 36.630ns, number of Slice LUT’s of 8113, power consumption of 115mW.