Jacobi solver is one of the most efficient to solve a large linear system of equations. As this method involves number of iterations, it takes a longer time for giving the solution in VLSI. This paper presents an implementation of Jacobi solver in FPGA, in which, the various blocks of Jacobi solver are implemented with Kogge-Stone adder (KSA) where ever addition is required. This resulted in an enhanced performance at the cost of little increase in area. The improvement in performance is a decrease in the delay of 67.7% in the minimum period of delay, which is a substantial improvement. As compared to the Ripple carry addition (RCA), addition implementation in the KSA is found to give an area savings of 21.21% in terms of slices, an area increase of 56.60% in terms of flip-flops and an increase of 49.04% in terms of 4 input LUTs. Hence this design can be implemented in places where high performance is of primary concern. The implementation and simulation have been performed in VHDL in Xilinx 14.7 targeted to FPGA.