This paper is published in Volume-4, Issue-3, 2018
Area
VLSI
Author
M. Revathy, S. Lavanya
Org/Univ
College of Engineering, Chennai, Tamil Nadu, India
Pub. Date
30 June, 2018
Paper ID
V4I3-2013
Publisher
Keywords
Canonical-Signed-Digit (CSD), Multiplier-free, Vector multiplication, Improved Signed Digit (ISD)

Citationsacebook

IEEE
M. Revathy, S. Lavanya. A regular and improved representation for signed digit constant vector multiplication, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.

APA
M. Revathy, S. Lavanya (2018). A regular and improved representation for signed digit constant vector multiplication. International Journal of Advance Research, Ideas and Innovations in Technology, 4(3) www.IJARIIT.com.

MLA
M. Revathy, S. Lavanya. "A regular and improved representation for signed digit constant vector multiplication." International Journal of Advance Research, Ideas and Innovations in Technology 4.3 (2018). www.IJARIIT.com.

Abstract

A novel improved signed digit representation procedure is proposed to overcome the two fundamental disadvantages of the current multiplier-free techniques: 1) circuit inconsistency and 2) computational redundancy. The fundamental difference between the existing multiplier free strategies and the proposed method could be a novel optimization framework based on vector decomposition. The constant vector is decomposed into two terms: a “private” matrix and a “public” vector which consist of the private operations of each individual entry and public operations shared by all of the entries, the overall data flow can be separated into two regular steps: first multiplied by the “public” vector and then by the “private” matrix. The computational complexity lessening task is then accomplished by minimizing the number of operations within the “private” matrix and the length of the “public” vector. Experimental results illustrate that the proposed strategy outflanks the existing multiplier free strategies in fewer operations and more regular circuit structure.