This paper represents a review of some existing clock gating techniques for low power dissipation in digital circuitry designs. In this paper, the clock gating techniques are used which reduces the power consumption from the normal implementation of the same design. The 16 bit ALU (arithmetic logical unit) is used for reducing the dynamic power consumption through gating techniques by shutting down the clock at a given instant of time when it is not needed for work to prevent the unnecessary power consumption of the system. These designs are implemented on RTL level at VIVADO 2016.4 platform for synthesis and simulation by different gating techniques.