A need for low power ICs arises to keep the power density of ICs within tolerable limits. While the power dissipation increases linearly with advanced version processors, the power density also increases exponentially, because of the ever-shrinking size of the integrated circuits. Reversible logic is emerging as an important research area in the recent years due to its ability to reduce power dissipation, which is the main requirement in low power digital design. In our proposed method reversible comparator based on CMOS logic circuit is designed using reversible gates. In this design, we try to reduce optimization parameters like a number of constant inputs, garbage outputs, and quantum cost. The experimental results obtained for implementation in CADENCE EDA 180nm technology shows the considerable reduction in terms of Power Delay Product in comparison with the comparator designed using conventional gates.