Nowadays in digital circuits, some important issues like high speed, high throughput, small silicon area, and low power consumption are being considered by designers. Full adders are important components in applications such as subtraction, counting multiplication, filtering, Digital Signal Processors (DSP) architectures, and microprocessors. so it at interest to design carry look ahead adder because of its high-speed operation and to study the functional behavior and power consumption. in this project, the CLA is implemented using 180nm CMOS technology in cadence virtuoso tool software. Two logics that is static CMOS and adiabatic logic have been analyzed and implemented. Finally, the power consumption is estimated and compared. from the results, power consumption will be found that adiabatic logic consumes low power whereas static CMOS logic offers low delay