With the advancement of CMOS technology, an outsized variety of transistors used thanks to that scaling happens. Currently on a daily basis memory plays a crucial role within the entire chip and provides the most power to the SOC system. during this paper, 6-T HVP, 7-T HVP, 8-T HVP and 9-T HVP is projected that improve the soundness of SRAM cell, reduce power in read-write operation and reduce escape power in standby mode. 2 techniques accustomed reduce power and escape power. In 1st technique offer voltage of one.1V is taken to look at the power within the overall circuit. In second technique offer voltage of one.1V is taken and voltage given to inputs is about to zero and thence power and escape the power of projected circuits are reduced. The Designed SRAM cells are compared to Existing SRAM cells in term of power, escape power, SNM, RSNM, PULL UP ratio (PR), CELL quantitative relation (CR), Temperature and Voltage. The simulation meted out in Tanner EDA tool with 32nm technology at 1V and CADENCE VIRTUOSO tool with 45nm technology at 1.1V power offer severally.