This paper is published in Volume-7, Issue-3, 2021
Area
Electronics and Communication
Author
Nagaraj N., Nithin M.
Org/Univ
RV College of Engineering, Bengaluru, Karnataka, India
Keywords
Setup time, Clock-to-Q delay
Citations
IEEE
Nagaraj N., Nithin M.. D Flip Flop circuits: Review of different architectures, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.
APA
Nagaraj N., Nithin M. (2021). D Flip Flop circuits: Review of different architectures. International Journal of Advance Research, Ideas and Innovations in Technology, 7(3) www.IJARIIT.com.
MLA
Nagaraj N., Nithin M.. "D Flip Flop circuits: Review of different architectures." International Journal of Advance Research, Ideas and Innovations in Technology 7.3 (2021). www.IJARIIT.com.
Nagaraj N., Nithin M.. D Flip Flop circuits: Review of different architectures, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.
APA
Nagaraj N., Nithin M. (2021). D Flip Flop circuits: Review of different architectures. International Journal of Advance Research, Ideas and Innovations in Technology, 7(3) www.IJARIIT.com.
MLA
Nagaraj N., Nithin M.. "D Flip Flop circuits: Review of different architectures." International Journal of Advance Research, Ideas and Innovations in Technology 7.3 (2021). www.IJARIIT.com.
Abstract
A detailed architectural study of different types of flip flop designs is presented. This includes the conventional transmission gate flip flop topology (TGFF), Sense amplifier-based flip flop architecture (SAFF), Clock pulse-based Flip Flop design, and the Dynamic Flip Flop architecture. The fundamental working principles of each topology are discussed along with the operation principles. Important comparisons are made between the architectures and are also presented as a part of this work.
