Basically, a conventional CMOS logic circuit design approach depends upon charging the output capacitive nodes to the supply voltage Vdd or discharging it to the ground. This is one of the most used methods in VLSI circuit designs. There are various techniques to design low power circuits to reduce power consumption. The major source of power dissipation is the charging and discharging of the capacitor. Whenever a capacitor is discharged to ground, an amount of energy stored in the capacitor is mislaid. We can reduce this power dissipation by restoring this energy to the source instead of discharging to the ground. It has been observed that by charging the capacitor gradually, the energy requirement is slighter than the faster charging method. The modern VLSI techniques focus significantly on High-Speed Propagation and Low Power Consumption. In this study, I present a low power 1-bit hybrid full adder design which utilizes both static CMOS logic and Swing Restoring Pass Transistor Logic. Moreover, a comparison is made on the power consumptions of various other designs with this work. The full adders are designed in Mentor Graphics 130nm technology. Starting at 0.4V supply, the average power consumed by this Hybrid design is 2.33µW.