Finite Impulse Response (FIR) Filter can be designed by provision of specifications which are for a particular application requirement. An efficient FIR filter is designed using register reduction retiming technique. Also, an optimization environment is designed such that filter components of post retimed circuit such as adder and multiplier are upgraded depending on the Very Large Scale Integration (VLSI) design metrics such as area, speed and power. In conventional cut-set retiming of FIR filter, higher critical path delay and latency occurs due to unwanted pipelining. They require higher clock period. So overcome, FIR filter it’s designed using Novel node – splitting and Node merging techniques. These schemes reduce the critical path delay by 50% and latency by 60%. In this paper node merging method is simulated and its performance parameters such as power, delay, critical path, latency, clock period and number of registers are analysed. In Data Flow Graph (DFG) retiming of digital circuit is used to reduce the propagation delay and critical path. The reduced propagation delay in turn reduces pipeline overheads. Thus, cut-set retiming can be made more efficient without increasing the register complexity and latency. The FIR architecture for node merging has to be designed and its performance is to be analysed. The proposed FIR filter using retiming technique are simulated using MODELSIM 10.1b and power analysis of the proposed work is done using Xilinx ISE 9.2i. In this proposed work the layout will be developed using AARON 9.03 tool.