This paper introduces a mixed-logic design method for line decoders, combining transmission gate logic, pass transistor dual-value logic and static CMOS. Two new topologies for the 2-4 decoder are 14-transistor topology and 15-transistor topology. 14-transistor topology based on the small size of the transistor, transistor count and power dissipation, 15-transistor topology based on high power-delay performance. Both non-inverting and inverting decoder are designed in every case thereby yielding a total of four new designs. Moreover, four new 4-16 decoders are designed, by using mixed-logic by cascading of 2-4 pre-decoders with static CMOS post-decoder. All proposed decoders which reduce transistor count and has the full swinging capability compared to conventional CMOS. GDI gate diffusion input analyses to design low power combinational circuits where we can overcome the disadvantages of CMOS, low power techniques.GDI technique helps to reduce power, propagation delay, transistor count, maintains the low complexity of designs. All proposed decoders are designed in Gate diffusion input (GDI)—a new technique of low-power digital combinatorial circuit design thereby results in reducing power consumption, propagation delay, and area of digital circuits while maintaining the low complexity of the logic design.