This paper is published in Volume-6, Issue-4, 2020
Area
VLSI Design
Author
Deepa S., Dr. Yasha Jyothi M. Shirur
Org/Univ
BNM Institute of Technology, Bengaluru, Karnataka, India
Keywords
FFT, Radix-2, Booth Multiplier, Fast Computation
Citations
IEEE
Deepa S., Dr. Yasha Jyothi M. Shirur. Design of flexible FFT core for fast computing of digital signals in real time applications, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.
APA
Deepa S., Dr. Yasha Jyothi M. Shirur (2020). Design of flexible FFT core for fast computing of digital signals in real time applications. International Journal of Advance Research, Ideas and Innovations in Technology, 6(4) www.IJARIIT.com.
MLA
Deepa S., Dr. Yasha Jyothi M. Shirur. "Design of flexible FFT core for fast computing of digital signals in real time applications." International Journal of Advance Research, Ideas and Innovations in Technology 6.4 (2020). www.IJARIIT.com.
Deepa S., Dr. Yasha Jyothi M. Shirur. Design of flexible FFT core for fast computing of digital signals in real time applications, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.
APA
Deepa S., Dr. Yasha Jyothi M. Shirur (2020). Design of flexible FFT core for fast computing of digital signals in real time applications. International Journal of Advance Research, Ideas and Innovations in Technology, 6(4) www.IJARIIT.com.
MLA
Deepa S., Dr. Yasha Jyothi M. Shirur. "Design of flexible FFT core for fast computing of digital signals in real time applications." International Journal of Advance Research, Ideas and Innovations in Technology 6.4 (2020). www.IJARIIT.com.
Abstract
To meet needs of the customers, real-time signals are processed dynamically in many of the wireless communications, audio/video processing and industrial control applications. The heart of any computation is DSP Processor. Traditionally, dedicated (application-specific) architectures are used for high performance DSP applications. This trend continues today as more digital signal processing and image/video processing algorithms are implemented on single chips. The three optimization factors which every designer will be concerned about are area, speed, and power. Out of which speed is an important factor to be considered in real-time applications. To facilitate the requirement of fast computing, a scalable and reusable FFT Processor is designed and verified for its functionality. In paper a radix-2 butterfly is designed and implemented for fast computation of digital signals which is scaled to perform 8-point DIT FFT and 16-point DIT FFT. The design also supports reconfigurability feature to meet the design specification.