In this paper low power, high-speed design of SET, DET, TSPC and C2CMOS Flip-Flop are designed and analyzed. As these flip-flops have a small area and low power consumption they can be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors etc. The Flip-Flops are analyzed at 90nm technologies. The above designed Flip-Flops and Latches are compared in terms of its transistor count, power dissipation and propagation delay using DSCH and Micro wind tools. This project proposes low power high-speed design of flip-flops in which True Single-Phase Clocking (TSPC) and C2CMOS flip-flop compared with existing flip-flop topologies in term of its transistor count, power dissipation, propagation delay, parasitic values with the simulation results in micro wind.