The PLL is a feedback system used to generate clock signal in microprocessors, and frequency multiplication (FM) etc., The PLL consists of several components such as Phase frequency detector (PFD), Charge pump (CP), low pass filter (LPF), voltage controlled oscillator (VCO) and frequency divider (FD) circuits. The struck at single-event-effects (SEEs) such as latch-up, single-event-transient and multiple bit upsets which affect the PLL performance. PFD and FD which are free from dead zone due to there digital characteristics but the CP are affected by SEEs which causes the CP output to be degraded and which affect the VCO input hence PLL will lose lock. The PLL and its components are implemented in cadence virtuoso tool using 180nm technology.