In early days of computers, multiplication was implemented generally with a sequence of addition, subtraction and shift operations. There exist many algorithms proposed in the literature to perform multiplication, each offering different advantages and having the trade-off in terms of delay, circuit complexity, area occupied on-chip and power consumption. Latency is the major issue of computing a function. Simply it’s a measure of how long the inputs to a device are stable is the final result available on outputs. Throughput is the measure of how many multiplications can be performed in a given period of time. The multiplier is not only a high delay block but also a major source of power dissipation. Normal multiplication process involves generation of partial products, an addition of partial products and finally, total product is obtained. So the performance of the multiplier depends on the number of partial products and the speed of the adder. The reversible computation is one field which assures zero power dissipation. Thus during the design of any reversible circuit, the delay is the only parameter that has to be taken care of. Hence reversible Urdhva Tiryakbhayam [UT] Multiplier had been proposed for reversible calculations. Vedic multiplier based on the Urdhva Tiryakbhayam algorithms provide the best results in terms of delay, area, and power.