The floating-point multiplier is designed to provide high precision and low power for scientific simulations, engineering computations, and financial modeling applications. This paper explains a single precision floating point multiplier architecture using a Vedic multiplier. It takes two single precision floating point numbers as input and produces a single precision hovering point number as output. The proposed architecture uses a pipelined approach to increase the speed of the multiplier and to reduce the power and delay. The pipeline architecture allows multiple operations to be performed simultaneously, resulting in a faster multiplication operation. The proposed architecture generates product mantissa by use of a Vedic multiplier with a carry-save adder using a Multiplexer to reduce the power of the multiplier. The proposed architecture is compared with array multiplier-based single precision floating point multiplier and performance measures such as power and delay. The architecture will be performed in Xilinx Vivado 2016.4 software by selecting the ZED board.