This paper introduces Full custom and RTL implementation of a Decimated audio range low pass filter has been implemented on programmable logic devices (FPGA/PROM/CPLD) as well as layout compatible to 1.2-µm n-well CMOS process for arithmetic circuit. The ADC can be operated with an oversampling clock frequency of up to 512 KHz & down sampling clock frequency of up to 8 KHz. An existing clock divider circuit has been used which divide the oversampling clock frequency by decimated factor 64(second-order).