This paper consists of a detailed review of five multipliers compared with respect to their parameters speed, area, power consumption, and circuit complexity namely are array multiplier, modified booth multiplier, Wallace multiplier, and modified booth Wallace multiplier also in this project experimental analysis of Multiplier and Accumulator (MAC) with the help of modified booth Wallace multiplier is proposed to perform the arithmetic operation with high speed, the performance was elevated when two operation multiplication and accumulation was combined and devised with the carry-save adder(CSA). Because of the accumulator propagation delay which is largest after merging CSA and MAC, it results in improved performance. Radix-2 modified booth algorithm based on 1’s complement has been used in proposed CSA design the bit density of multiplier and multiplicand are going to increase by using the modified booth algorithm. To decrease the number of input bits, carries propagates through the LSB of partial products so has to generate the LSB in advance. A pipeline scheme has been introduced in the architecture proposed for MAC in order to accumulate the intermediate result in the form of sum and carry so that the performance of architecture gets improved. While keeping the clock frequency the same the proposed architecture is twice efficient as of previous design