The necessity for ultra-low-power, high speed, and area efficient analog-to-digital converters is driving toward the use of dynamic regenerative comparators to maximize speed and power regulation. This paper describes the Double Tail Dynamic Comparator designed in 180nm CMOS Technology. The circuit works on very less power supply of 200mV. The power dissipation of the circuit is approx. 160 nW. The slew rate of the circuit is quite high. The design work at the 1 GHz of frequency it is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced.