Ensuring correct operation of design despite rising levels of design complexity has been a major focus of research and development since the dawn of digital system design. As design size and complexity increase, so is the need to verify designs quickly and reliably. This, combined with the reduced design cycle of 3-6 months, makes verification an extremely challenging task. Once the chip is taped out, if the chip is not meeting timing or if the chip is consuming too much power then it is a big issue and results in huge loss. So in order to avoid these post silicon surprises, preliminary signoff checks are must. This paper covers the various kinds of timing quality checks that are used in the industry including the checks related to connectivity, clock, Max slope and Max capacitance, checks for Latch etc. Also in advanced technology nodes one has to consider the effect of PVT variation, temperature inversion, noise effect on delay, which is adding more scenarios for STA to cover. With big SOC project, one timing ECO run normally takes 3~5 days. The turn-around-time for timing ECO and timing signoff has become a bottle neck in the later stage of the project. So there is an immense need of effective implementation of ECO with new technologies including physically aware ECO with less resource, reduced design cycle time and reduced manual effort. The proposed algorithm is tested on multiple industrial design and found to achieve good improvement interms of Worst Negative Slack, Total Negative Slack and Failing End Points. Also the algorithm is physically aware meaning that the placement blockages, congestions are considered while inserting buffers. The algorithm works under Distributed Multi Scenarios Analysis (DMSA) environment and considers the effect of ECO across multiple corners and modes.