These days controlling the variation in device parameters during fabrication is a great challenge. The variations in process parameters such as the oxide thickness, channel length, and width, and doping in a channel result in a large change in threshold voltage. This process variation on design metrics of Static Random Access Memory (SRAM) cell which is used for process-tolerant cache architecture is suitable for complex memory design. The six-transistor and seven-transistor SRAM cells have been used to find the impact of process variation at 32nm technology. The 7T SRAM bit cell has a 60% improvement in SNM at the cost of area penalty, power penalty, read delay penalty, and variability penalty. This shows that the 6T SRAM cell is more efficient than the 7T cell.