This paper presents a design of Low power 4 bits Counter at circuit and system level of abstraction using Cadence Virtuoso and Xilinx ISE 14.7 respectively. The laboratory work described includes the CMOS based transistor level design and VHDL based synthesis and implementation of the counter using back end and front end tools respectively. The functionality of the design has been simulated and tested using 0.18µm gdpk CMOS technology with 1.8V supply voltage using cadence virtuoso for back-end designing whereas, Xilinx ISE 14.7 is used for front-end simulation, synthesized using plan¬-ahead and is implemented on ArtixTM-7(family), with device xC7A100TTM. Power calculation has been done at 100 MHz clock frequency for the 1.8V supply voltage.