Now a day’s arithmetic circuit plays an important role in designing of any VLSI system. Such as subtractor is one of them. In this paper, half-subtractor is designed by using the adaptive voltage technique (AVL). By using the AVL technique, half subtractor can reduce the power and delay element. We can reduce the value of total power dissipation by applying the AVLG (adaptive voltage level at ground ) technology in which the ground potential is raised and AVLS (adaptive voltage level at supply) in which the supply potential is increased. The AVL technique shows the significant reduction in power consumption and propagation delay. The circuit is simulated on cadence tool in 180 nanometre CMOS technology.