In this paper, a high performance adder is designed for low power application. Carry Select Adder (CSLA) is known to be the fastest adder among the conventional adder structures. It is used in many data processing units for realizing faster arithmetic operations. From the structure of the CSLA, it is clear that there is scope for reducing power consumption and delay in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the power and delay of the CSLA. Based on this modification, 16-bit CSLA architecture have been developed and compared with the regular CSLA architecture. The results analysis shows that the proposed CSLA structure is better than the regular CSLA.