One-bit full-adder efficiency and interpretation are anatomized into smaller parts. Such modules are thoroughly tested. Multiple designs are created, simulated and evaluated for each full adder. Twenty separate 1-bit full-adder modules are designed by integrating the various designs of these modules. Each of these full adder exhibits different power consumption, speed, area, and driving capabilities. Two realistic circuit structures that include full adders are used for simulation. The main aim of our project is to use CMOS technology to construct an optically reconfigurable low power full adder circuit. Analysis of time parameters in all existing full adders and comparison with the time study of our proposed circuit.