This paper is published in Volume-3, Issue-1, 2017
Area
Electronics and Communication Engineering
Author
Dr. M. Nizamuddin
Org/Univ
Baba Ghulam Shah Badshah University, Rajouri, J&K, India
Keywords
CMOS Comparator, Low Power, High Speed, ADC and HSPICE-
Citations
IEEE
Dr. M. Nizamuddin. Simulation Study of Low Power Comparator for A-D Converter, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.
APA
Dr. M. Nizamuddin (2017). Simulation Study of Low Power Comparator for A-D Converter. International Journal of Advance Research, Ideas and Innovations in Technology, 3(1) www.IJARIIT.com.
MLA
Dr. M. Nizamuddin. "Simulation Study of Low Power Comparator for A-D Converter." International Journal of Advance Research, Ideas and Innovations in Technology 3.1 (2017). www.IJARIIT.com.
Dr. M. Nizamuddin. Simulation Study of Low Power Comparator for A-D Converter, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.
APA
Dr. M. Nizamuddin (2017). Simulation Study of Low Power Comparator for A-D Converter. International Journal of Advance Research, Ideas and Innovations in Technology, 3(1) www.IJARIIT.com.
MLA
Dr. M. Nizamuddin. "Simulation Study of Low Power Comparator for A-D Converter." International Journal of Advance Research, Ideas and Innovations in Technology 3.1 (2017). www.IJARIIT.com.
Abstract
Abstract- Analog-to-Digital Converters (ADCs) translate the analog quantities into digital language, used in information processing, computing, data transmission and control systems. ADCs are key components for the design of power limited systems, in order to keep the power consumption as low as possible. Implantable Medical electronics, such as Pacemakers and cardiac defibrillators are typical examples of devices where ultra-low-power consumption is paramount. This paper presents the design of CMOS comparator based on a preamplifier circuit. The design is intended to be implemented in for Analog-to-Digital Converter (ADC). The design is simulated in 1 μm CMOS Technology with HSPICE. Proposed design exhibits low power consumption. Simulation results are presented and the design has DC Gain of 68dB, the power dissipation of 1.25 mW at 5 V.