Skew is one of the most important parameters that decides the performance of the system.Though skew is reduced using two-stage serially connected power mode aware buffers using two power gating techniques, power consumption and area is considerably larger in fine grain power gating. So, in the proposed system, coarse grain minimization is used at both stages which will effectively reduce power consumption and area.The coarse grain approach implements the grid style sleep transistors which drive cells locally through shared virtual power networks.This approach is less sensitive to PVT variation, introduces less IR drop and imposes a smaller area overhead than the cell or cluster based implementations.In coarse grain power gating, transistor is a part of the power distribution network rather than the standard cell