Three Dimensional Integrated Circuits (3D IC) have been getting attention among researchers and IC designers as an emerging technology to help overcome the interconnect delay and power limitations. Tight integration of multiple silicon tiers using vertical 3D vias as interconnect offers a better functioning of 3D-ICs. In this work, we focus on 3D-SICs implemented using Through- Silicon Via (TSV) vertical interconnects. Through strategic modification of the architectures to take advantage of 3D, significant improvement in the functioning can be achieved.