Static Random Access Memory (SRAM) is the important component across a wide range of microelectronics applications like high performance server processors, multimedia and System on Chip (SoC). The lower power consumption, static noise margin (SNM), read and write stability are the major design metrics for designing an SRAM cell. It is difficult to achieve that conventional 6 T SRAM cell in scaled technology, particularly in deep-subthreshold region. In this paper, impact of process parameters variations on various design metrics of the proposed cell are presented and compared with conventional 6T and 8T.The proposed 9T cell utilizes a scheme with separate read and write word lines it is shown that the 9T cell achieves improvements in power dissipation, performance and stability compared with previous designs (that require 6T and 8T) for low-power operation. The 9T scheme is amenable to small feature sizes as encountered in the deep sub-micron/nano ranges of CMOS technology. The proposed 9T SRAM cell designed in 130 nm Complementary Metal Oxide Semiconductor (CMOS) technology in the power supply voltage of 1.8 V. The simulation is done by using AARON 9.03 tool to achieve the power consumption of 91.55% lesser than existing method, Then the read and write delay of proposed 9T SRAM cell is reduced by 8.3% and 23.0% lesser than conventional 6T and 8T.